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We develop advanced architectures for memory and transistors, focused on stability, energy efficiency and scalability for high-performance systems.
Infrastructure for AI
The growth of artificial intelligence, HPC and autonomous systems demands new device-level architectures: more stable memories, more efficient transistors and technologies capable of operating under energy limits, thermal limits and structural constraints that are increasingly strict.
Our technologies
ReRAM/VCM memory architecture designed to reduce random telegraph noise, improve read stability and enable non-volatile memory for the next generation.
See RTN-Null CellGAA-FET gate architecture for sub-2nm nodes, focused on addressing direct tunneling leakage and extending energy efficiency in the Angstrom era.
See HyperGateTwo architectures. One shared vision: extend the physical limits of modern computing from memory, transistor and technology transfer.
Start the conversationArchitecture designed to improve ReRAM stability through reduced noise, variability and operational degradation.
Gate stack architecture designed for advanced GAA-FET processes, focused on electrostatic control and gate leakage reduction.
We design semiconductor technologies with a clear vision: build the infrastructure that will make the next generation of computing possible.
Each architecture addresses real industry challenges, from energy efficiency and scalability to the integration of systems that are becoming more and more complex.
Architectures designed to respond to growing computational demand in AI, HPC and other high-performance systems.
Solutions aimed at reducing electrical losses, improving operating efficiency and optimizing consumption at the device level.
Approach based on standard CMOS materials and processes to reduce barriers to adoption in advanced manufacturing.
Technical collaboration path for electrical characterization, comparative evaluation and development under NDA.
Open model for different paths of collaboration, integration, licensing, partial transfer, joint development or other negotiated structures depending on the case.
Collaboration process
We do not start from a fixed commercial modality. We analyze the technical, strategic and operational needs of each organization to define a suitable collaboration structure, protecting the technology and keeping negotiation options open.
We analyze the use case, constraints, hardware environment, performance objectives, strategic priority and possible integration scenarios.
We define a technical test under agreed conditions, with metrics for stability, precision, traceability, performance and comparison against existing benchmarks.
The modality is defined after understanding the value created. It may include technology integration, joint development, partial transfer of rights, limited exclusivity or another negotiated structure.
Once the scope is defined, rights, usage limits, duration, territories, sectors, technical access, confidentiality and implementation conditions are formalized.
Validation and collaboration
TERACT seeks to collaborate with research centers, foundries, fabless teams, industrial partners and deep-tech investors to validate its architectures through electrical characterization, test lots and comparative analysis under confidentiality agreements.
Request a technical conversationContact
If you represent a semiconductor company, research center, deep-tech fund or strategic partner, share your interest and we will prepare the right conversation for technical validation, strategic collaboration or the right commercial structure for the case.
Complete the form and we will prepare the right conversation for NDA, technical validation, commercial structure, strategic collaboration or industrial integration.