GAA-FET architecture designed to address direct tunneling leakage and extend energy efficiency in advanced nodes.
The problem
The transition toward sub-2nm nodes requires maintaining electrostatic control while the interfacial layer and equivalent oxide thickness shrink to extremely small scales.
At these dimensions, the probability that electrons tunnel through the gate can grow significantly, increasing leakage current and standby power consumption.
This phenomenon limits scaling, increases the thermal challenge and affects the energy viability of advanced chips for AI, HPC and mobile devices.
The solution
HyperGate V40 proposes a GAA-FET gate architecture based on dimensional control of the interfacial layer and its interaction with the high-k, oriented toward reducing leakage and preserving performance.
Configuration designed to maintain functional isolation and channel control at dimensions where traditional scaling begins to fail.
Use of standard materials such as SiO2 and HfO2 within an architecture optimized for advanced transistor processes.
Design oriented to reduce leakage current without sacrificing the electrostatic control required for next-generation nodes.
Approach prepared for foundries, PDKs and GAA-FET processes in the transition toward the Angstrom era.
Expected advantages
The advantages described represent expected technical targets and must be validated through test wafers, C-V/I-V characterization and comparison against control lots.
Architecture focused on reducing gate leakage and static power consumption in high-density designs.
Lower electrical losses can translate into a better thermal budget and higher efficiency per operation.
Design oriented to reduce penalties associated with the interaction between channel, interface and high-k dielectric.
Use of SiO2, HfO2 and existing industrial processes to support a realistic adoption path.
Target market
HyperGate V40 is aimed at organizations that develop, fabricate or integrate advanced chips where energy efficiency and scaling are critical factors.
Possible integration into advanced GAA-FET nodes through technical collaboration, test wafers and process validation.
Architecture oriented toward high-performance chips for AI, mobile, GPUs, CPUs and intensive computing systems.
Reduction of electrical losses to improve performance per watt in massive computing workloads.
Potential contribution to lower energy consumption, lower heat generation and better operational efficiency at scale.
Validation path
Validation must demonstrate reduced gate leakage, stable electrostatic control and repeatable behavior versus reference structures.
Fabrication of a test lot with the interfacial layer and gate stack defined for initial electrical evaluation.
Whitepaper and technical contact
Share your technical or strategic interest to review the whitepaper, evaluate a joint validation path or explore integration into advanced processes under NDA.
Technical contact
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