TERACT · RTN-Null Cell
Product view for preliminary review. It presents functional layers, expected KPIs and an expanded experimental path without disclosing exact geometry, fine composition or figures reserved for confidential material.
Stack scheme
The stack is organized by electrical and interfacial functions. The intention is to control vacancy dynamics and preserve read stability during operation.
Metal interface aimed at stable and reproducible contact with standard process materials.
Region designed to enable resistive switching under a controlled distribution of active defects.
Layer with structural and electrical support function, oriented to contain leakage and stabilize the functional interface.
Base compatible with BEOL integration and comparative evaluation against control cells.
Expected KPIs
These indicators represent performance hypotheses and must be validated through test lots, statistical analysis and comparison against reference structures.
Lower dispersion across cycles and a more consistent read window in HRS.
Reduced RTN/TLS signatures under operating conditions relevant to resistive memory.
Better conditions to explore stable intermediate states in MLC/TLC schemes.
Expanded experimental path
Expanded validation is posed as a staged process, with emphasis on repeatability, interfaces and comparison against control.
Fabrication of experimental and control devices under nearby process windows, to separate architectural effect from manufacturing variation.
I-V reads, resistive state distribution, temporal stability and behavior under repeated programming sequences.
Observation of RTN/TLS signatures, interfacial behavior and correlation with resistance states in operation.
Review of compatibility with CMOS BEOL sequences, standard materials and possible industrial adoption limitations.
Next step
Complete documentation and any discussion of reserved parameters are handled through direct request and, when applicable, under NDA.